RISC-V IOMMU series unlocks MSI remap, DMA, and VFIO assign

A 21-patch series from Andrew Jones aims to bring RISC-V IOMMU support in line with other major architectures for DMA isolation and virtual machine device assignment.

The core gap was MSI handling. On RISC-V, a device’s interrupt target address changes with CPU affinity, so MSI writes could not simply share the same translated path as ordinary DMA. Without that, the kernel could not turn on IOMMU_DMA and paging domains by default. The series introduces interrupt-remapping support for the IMSIC, mapping MSI targets into each device’s DMA address space so composed messages go through the IOMMU like other traffic. Tomasz Jeznach’s follow-on change then enables IOMMU_DMA for 64-bit RISC-V.

That plumbing also unblocks VFIO and iommufd. The driver now reports cache-coherency capability for DMA-coherent devices, VFIO type1 and KVM VFIO are opened for RISC-V, and defconfig builds iommufd and VFIO as modules. Generic VFIO selftests gain a riscv64 build target. In practical terms, PCIe devices can be assigned into KVM guests on RISC-V the way they already can on x86, arm64, and s390.

Limits remain. The RISC-V IOMMU specification does not validate MSI data, so the remapping path cannot offer isolated MSI; assignment still needs the allow_unsafe_interrupts module parameter. Direct MSI delivery into guest interrupt files (irqbypass) is left for a later series.

On the linux-kernel list, Jason Gunthorpe reviewed the coherency reporting but pushed back on the MSI design. He argued iommufd already owns software MSI mapping, questioned rebuilding domain-local IOVA tables on attach, and preferred extending the existing ARM-style prepare path to cover the full set of affinity target pages rather than pre-mapping inside the IOMMU driver.